1. Field of the Invention
The present invention relates to a method of manufacturing a power device, and more particularly, to a method for manufacturing a power semiconductor device capable of improving uniform distribution of electric field.
2. Description of the Prior Art
Power devices are typical semiconductor devices in power management applications, such as a switching power supply, a power control IC of a computer system or peripherals, a power supply of a backlight, motor controller, etc. Power devices can include various kinds of transistors, such as an insulated gate bipolar transistor (IGBT), a metal-oxide-semiconductor field effect transistor (MOSFET) and a bipolar junction transistor (BJT).
Furthermore, developments of trench power MOSFETs become an important tendency, because trench power MOSFETs can provide a lower electric resistance in conduction and a smaller device dimension, and can effectively control voltages with the fewer power-consumption. As shown in FIG. 1, a trench power MOSFET 10 includes an n+ type semiconductor wafer substrate 12. An n- type semiconductor layer 14 is formed on the semiconductor wafer substrate 12 by epitaxy. A first trench 16, a plurality of second trenches 18, a p type body 20, a plurality of p+ type regions 21, and a plurality of n+ type source regions 22 are formed in the semiconductor layer 14. A gate oxide layer 32 and a polysilicon material 34 are disposed within the first trench 16 and the second trenches 18. The polysilicon material 34 serves as a gate of the trench power MOSFET 10. The power device further includes an interlayer dielectric 24 covering the p type base 20, the gate, and the source regions 22. A gate metal layer 26 is disposed on the interlayer dielectric 24 and connects with the gate within the first trench 16 through a contact plug 28. A source metal layer 27 is disposed on the interlayer dielectric 24 and connects with the source regions 22 and the p+ type regions 21 through a plurality of contact plugs 30. A drain metal layer 36 is disposed on the other side of the semiconductor wafer substrate 12.
The desire for ever more compact electronic devices has pushed for size reductions in integrated circuits. Therefore, higher integrations and higher densities are developed continuously. The layout design for the conventional trench power MOSFET 10 structure has been investigated to reduce the trench width and the trench pitch. However, the layout design already reaches the process limitation. For example, there is a process limitation for the contact plug electrically connecting the gate, such that the opening for forming the contact plug must have a certain width for filling with material such as tungsten to form the contact plug. Accordingly, it is required for the first trench 16 to have a certain width, such as 0.8 micron, for forming the gate to provide a sufficient top surface area for the contact plug to be formed thereon. However, since the second trenches 18 are formed without contact plugs disposed thereon, the trench width can be narrower, for example, 0.2 micron. The first trench 16 and the second trenches 18 are usually formed simultaneously through an etching process. When the trench width is wider, the trench depth becomes deeper. It is because the wider trench is etched in a faster rate due to loading effect. As the depths of all the portions of the p type base 20 are the same, the deeper gate trench will lead to a stronger electric field, such that the electric field as a whole on the substrate is not uniform. Moreover, stronger electric field leads to a reduced breakdown voltage. One conventional solution is to sacrifice the resistance at and near by the p-n junction for increasing the breakdown voltage to a predetermined value. However, the reliability is affected. Another conventional solution is to form a ring-shaped guard ring doped region around the first trench 16. For example, as shown in FIG. 2, the conventional trench power MOSFET 11 further has a guard ring doped region 38. The guard ring doped region 38 is doped with a p− type dopant with a low concentration, in order to lower the position of the junction to reduce resistance. However, in the conventional process for forming such guard ring doped region, a mask is required to cover the region other than the guard ring doped region, resulting in an increased manufacturing cost, which is described in detail as follows.
In a conventional method of fabricating power semiconductor device, an active area is defined on a semiconductor substrate using a mask, followed by some main steps using masks as shown by the flow chart in FIG. 3. For example, in step 2, forming a guard ring doped region at a predetermined location by doping in the active area in the semiconductor substrate using a mask. In step 3, a gate trench is formed by etching the semiconductor substrate using a mask. In step 4, polysilicon is deposited to fill up the trench and etched back. In step 5, n type and p type doping processes are performed using masks respectively to obtain desired p base, p+ type regions, and source region. After formation of interlayer dielectric, step 6 is performed to form contact plugs by forming through holes in the interlayer dielectric using a mask and filling tungsten metal in the through holes. In step 7, the metal layer on the interlayer dielectric is patterned using a mask to form a source metal layer and a gate metal layer. Generally, in a conventional standard fabrication process, 7 masks are required. Especially, in step 2, a mask is required for forming a guard ring doped region, and it is costly.
Accordingly, it is still needed for a novel method of fabricating power semiconductor device to conveniently and economically resolve or mitigate the problem of non-uniform electric field as aforesaid and maintain high and stable breakdown voltage.